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19-2856; Rev 0; 4/03
Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout
General Description
The MAX9178 quad low-voltage differential signaling (LVDS) line driver with high-ESD tolerance is ideal for applications requiring high data rates and low power with reduced noise. The MAX9178 is guaranteed to transmit data at speeds up to 400Mbps (200MHz) over controlled impedance of media of approximately 100. The transmission media can be printed circuit (PC) board traces, backplanes, or cables. The MAX9178 accepts four LVTTL/LVCMOS inputs and translates them to LVDS output signals. All inputs tolerate overshoot of VCC +1V and undershoot of -1V. The EN and EN inputs are ANDed together and control the high-impedance outputs. When the device is disabled, power drops to ultra-low 12.6mW (typ). Outputs conform to the ANSI TIA/EIA-644 LVDS standard. The MAX9178 operates from a single +3.3V supply, and is available in a 16-pin TSSOP and 16-pin thin QFN package with exposed pad. The MAX9178 is specified for operation from -40C to +85C.
Features
o Flow-Through Pinout Simplifies PC Board Layout Reduces Crosstalk o Pin Compatible with DS90LV047A and MAX9123 o Guaranteed 400Mbps Data Rate o Single-Ended Inputs Tolerate 1V Overshoot/Undershoot o 250ps Maximum Pulse Skew o IEC 61000-4-2 Level 4 ESD Tolerance on LVDS Outputs o Conforms to ANSI TIA/EIA-644 LVDS Standard o Single +3.3V Supply
MAX9178
Ordering Information
PART MAX9178EUE MAX9178ETE TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 TSSOP 16 Thin QFN-EP*
Applications
Digital Copiers Laser Printers Cell Phone Base Stations Add/Drop Muxes Digital Cross-Connects DSLAMs Network Switches/Routers Backplane Interconnect Clock Distribution
*EP = Exposed pad.
Typical Application Circuit
LVDS SIGNALS MAX9122
MAX9178
Functional Diagram appears at end of data sheet.
TX
107
RX
Pin Configurations
OUT1+ OUT1-
TX
107
RX
TOP VIEW
IN1 16 EN 1 IN1 2 IN2 3 VCC 4 GND 5 IN3 6 IN4 7 EN 8 16 OUT115 OUT1+ 14 OUT2+ 13 OUT2VCC GND IN3 2 3 4 5 IN4 6 EN IN2 1 15 EN
14
13
LVTTL/CMOS DATA INPUT
LVTTL/CMOS DATA OUTPUT
12 OUT2+ 11 OUT2-
TX
107
RX
MAX9178
12 OUT311 OUT3+ 10 OUT4+ 9 OUT4-
MAX9178
EXPOSED PAD
10 OUT39 OUT3+
TX
7 OUT48 OUT4+
107
RX
TSSOP
QFN
100 SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
________________________________________________________________ Maxim Integrated Products
1
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Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout MAX9178
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V IN_, EN, EN to GND....................................-1.4V to (VCC + 1.4V) OUT_ to GND ........................................................-0.3V to +4.0V Short-Circuit Duration (OUT_) ....................................Continuous Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 9.4mW/oC above +70C) .........755mW 16-Pin QFN (derate 16.9mW/oC above +70C) .........1349mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C ESD Protection Human Body Model All Pins to GND ............................................................2kV OUT_ ............................................................................2kV IEC 61000-4-2 Level 4 Contact Discharge (OUT_)...............................................8kV Air Discharge (OUT_) .....................................................15kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, IN_ = high or low, EN = high, EN = low, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER LVDS OUTPUTS (OUT_+, OUT_-) Differential Output Voltage Change in Magnitude of VOD Between Complementary Output States Offset Voltage Change in Magnitude of VOS Between Complementary Output States Output High Voltage Output Low Voltage Unterminated Output High Voltage Unterminated Output Low Voltage Differential Output Short-Circuit Current Magnitude Output Short-Circuit Current Output High-Impedance Current Power-Off Output Current INPUTS (IN_, EN, EN) High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.0 -1.0 VCC + 1 +0.8 V V VOD VOD VOS VOS VOH VOL VOHUT VOLUT IOSD IOS IOZ IOFF Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Output open, Figure 6 Output open, Figure 6 VOD = 0 (Note 3) OUT_+ = 0 at IN_ = high, or OUT_- = 0 at IN_ = low EN = low and EN = high, OUT_ = 0 or VCC, no load VCC, IN_, EN, EN = 0 or open, OUT_ = 0 or 3.6V, no load -0.5 -0.5 0.002 0.001 0.90 1.9 0.1 9 -9 +0.5 +0.5 1.125 250 368 0.3 1.28 0.3 450 25 1.375 25 1.6 mV mV V mV V V V V mA mA A A SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL = 100 1%, IN_ = high or low, EN = high, EN = low, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER Input Current SUPPLY CURRENT ICC Supply Current ICCL ICCZ IN_ = VCC or 0, EN = VCC, EN = 0, no load IN_ = VCC or 0, EN = VCC, EN = 0, outputs loaded IN_ = VCC or 0, EN = 0, EN = VCC 3.8 18 3.8 6.0 25 6 mA SYMBOL IIN CONDITIONS 0 IN_, EN, EN VCC VCC IN_, EN, EN VCC + 1 -1V IN_, EN, EN 0 -1.5 MIN -20 TYP 5 0.67 -0.46 MAX +20 1.5 UNITS A mA
MAX9178
SWITCHING CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, CL = 15pF, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 4-7)
PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew Differential Channel-to-Channel Skew Differential Part-to-Part Skew Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Active to High Time High to Active Time Maximum Operating Frequency SYMBOL tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tR tF tPHZ tPLZ tPZH tPZL tAH tHA fMAX Figures 2, 3 Figures 2, 3 Figures 2, 3 (Note 8) Figures 2, 3 (Note 9) Figures 2, 3 (Note 10) Figures 2, 3 (Note 11) Figures 2, 3 Figures 2, 3 Figures 4, 5 Figures 4, 5 Figures 4, 5 Figures 4, 5 RL = 80 to 132 1%; Figures 6, 7 RL = 80 to 132 1%; Figures 6, 7 (Note 12) (Note 13) 200 0.20 0.20 0.43 0.41 3.9 3.9 5.0 5.0 50 1.0 CONDITIONS MIN 0.9 0.9 TYP 1.4 1.5 0.1 0.15 MAX 2.0 2.0 0.25 0.35 0.9 1.1 0.70 0.70 5 5 7 7 100 1.5 UNITS ns ns ns ns ns ns ns ns ns ns ns ns s MHz
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +85C. Note 2: Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except VOD, VOD, VOS, and VOS. Note 3: Guaranteed by design. Note 4: AC parameters are guaranteed by design and characterization. Limits are set at 6 sigma. Note 5: CL includes probe and jig capacitance. Note 6: Pulse generator output for AC tests: tR = tF = 1ns (0.2 x VCC to 0.8 x VCC), 50% duty cycle, RO = 50, VOH = VCC + 1V settling to VCC, VOL = -1V settling to zero, frequency = 200MHz. _______________________________________________________________________________________ 3
Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout MAX9178
SWITCHING CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL = 100 1%, CL = 15pF, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 4-7) Note 7: Pulse generator output for tPHZ, tPLZ, tPZH, tPZL, tAH, and tHA tests: tR = tF = 1ns (0.2 x VCC to 0.8 x VCC), 50% duty cycle, RO = 50, VOH = VCC + 1V settling to VCC, VOL = -1V settling to zero, frequency = 100kHz. Note 8: tSKD1 is the magnitude of the difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|. Note 9: tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device. Note 10: tSKD3 is the magnitude of the difference of any differential propagation delays between devices at the same VCC and within 5C of each other. Note 11: tSKD4 is the magnitude of the difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. Note 12: After tHA time, all switching characteristics specifications are met. Note 13: Meets all AC parameters at fMAX = 200MHz with |VOD | 250mV.
Typical Operating Characteristics
(VCC = +3.3V, RL = 100, CL = 15pF, TA = +25C, unless otherwise noted.)
OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE
MAX9178 toc01
OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT (mA) VIN = VCC OR GND -3.4
MAX9178 toc02
5.0 OUTPUT SHORT-CIRCUIT CURRENT (mA) VIN = VCC OR GND 4.6
-3.0
4.2
-3.8
3.8
OUT_ TO GND
-4.2 OUT_ TO VCC -4.6
3.4
3.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
-5.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
OUTPUT HIGH-IMPEDANCE STATE CURRENT vs. SUPPLY VOLTAGE
MAX9178 toc03
DIFFERENTIAL OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
DIFFERENTIAL OUTPUT VOLTAGE (mV) 368 366 364 362 360 358 356 354 352
MAX9178 toc04
90 OUTPUT HIGH-IMPEDANCE CURRENT (pA) OUT_ TO GND 60
370
30
0
-30
OUT_ TO VCC
-60 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
350 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
4
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Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL = 100, CL = 15pF, TA = +25C, unless otherwise noted.)
MAX9178
DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTOR
MAX9178 toc05
OFFSET VOLTAGE vs. SUPPLY VOLTAGE
1.278 1.276 OFFSET VOLTAGE (V) 1.274 1.272 1.270 1.268 1.266 1.264 1.262
MAX9178 toc06
SUPPLY CURRENT vs. FREQUENCY
MAX9178 toc07
600 DIFFERENTIAL OUTPUT VOLTAGE (mV) 500 400 300 200 100 0
1.280
27
SUPPLY CURRENT (mA)
24
21 ALL-CHANNELS SWITCHING 18 ONE-CHANNEL SWITCHING 15 0.01
1.260 50 60 70 80 90 100 110 120 130 140 150 LOAD RESISTOR () 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
0.1
1
10
100
1000
FREQUENCY (MHz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9178 toc08
SUPPLY CURRENT vs. AMBIENT TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ns) FREQUENCY = 200MHz 26 SUPPLY CURRENT (mA) ALL-CHANNELS SWITCHING
MAX9178 toc09
DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
FREQUENCY = 200MHz 1.50 1.45 1.40 1.35 1.30 1.25 tPHLD tPLHD
MAX9178 toc10
30 FREQUENCY = 200MHz 28 SUPPLY CURRENT (mA) 26 ALL-CHANNELS SWITCHING 24 22 20 ONE-CHANNEL SWITCHING 18 16 3.0 3.1 3.2 3.3 3.4 3.5
28
1.55
24
22
20
ONE-CHANNEL SWITCHING
18 3.6 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) TEMPERATURE (C)
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY vs. AMBIENT TEMPERATURE
MAX9178 toc11
DIFFERENTIAL SKEW vs. SUPPLY VOLTAGE
MAX9178 toc12
DIFFERENTIAL SKEW vs. AMBIENT TEMPERATURE
180 160 DIFFERENTIAL SKEW (ps) 140 120 100 80 60 40 20 0 FREQUENCY = 200MHz
MAX9178 toc13
2.0 DIFFERENTIAL PROPAGATION DELAY (ns) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 -40 -15 10 35 60 tPLHD tPHLD FREQUENCY = 200MHz
200 180 160 DIFFERENTIAL SKEW (ps) 140 120 100 80 60 40 20 0 FREQUENCY = 200MHz
200
85
3.0
3.1
3.2
3.3
3.4
3.5
3.6
-40
-15
10
35
60
85
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
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5
Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout MAX9178
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL = 100, CL = 15pF, TA = +25C, unless otherwise noted.)
TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9178 toc14
TRANSITION TIME vs. AMBIENT TEMPERATURE
FREQUENCY = 200MHz 450
MAX9178 toc15
550 FREQUENCY = 200MHz 500 TRANSITION TIME (ps)
500
TRANSITION TIME (ps)
tR
450 tR 400 tF
400
tF
350
350
300 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
300 -40 -15 10 35 60 85 TEMPERATURE (C)
Pin Description
PIN TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -- QFN 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 EP NAME EN IN1 IN2 VCC GND IN3 IN4 EN OUT4OUT4+ OUT3+ OUT3OUT2OUT2+ OUT1+ OUT1Exposed Pad FUNCTION LVTTL/LVCMOS Enable Input. All outputs are disabled when EN is low. Internally pulled down. LVTTL/LVCMOS Input 1. Input internally pulled down. LVTTL/LVCMOS Input 2. Input internally pulled down. Power-Supply. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. Ground LVTTL/LVCMOS Input 3. Input internally pulled down. LVTTL/LVCMOS input 4. Input internally pulled down. LVTTL/LVCMOS Inverting Enable Input. All outputs are disabled when EN is high. Internally pulled down. Inverting LVDS Output 4 Noninverting LVDS Output 4 Noninverting LVDS Output 3 Inverting LVDS Output 3 Inverting LVDS Output 2 Noninverting LVDS Output 2 Noninverting LVDS Output 1 Inverting LVDS Output 1 Exposed Pad. Solder to ground plane.
6
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Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout
Test Circuits/Timing Diagrams
CL OUT_+ 2V TO VCC + 1 -1V TO 0.8V IN_ VOD RL / 2 OUT_VOS 50 CL RL / 2 PULSE GENERATOR IN_ RL OUT_ OUT_ +
MAX9178
Figure 1. Driver VOD and VOS Test Circuit
Figure 2. Transition Time and Propagation Delay Test Circuit
VCC + 1V VCC 0.5 x VCC 0.5 x VCC 0 tPLHD tPHLD -1V
IN_
OUT_0 (DIFFERENTIAL) OUT_+ 0 (DIFFERENTIAL)
VDIFF
20% tR
80% 80% 0 (DIFFERENTIAL) VDIFF = (OUT_+) - (OUT_-) tF
0 (DIFFERENTIAL) 20%
Figure 3. Transition Time and Propagation Delay Waveform Timing
CL OUT_+ 2V TO VCC + 1V -1V TO 0.8V IN_ +1.2V RL / 2 OUT_CL EN PULSE GENERATOR 50 EN RL / 2
1/4 MAX9178
Figure 4. High-Impedance Delay Test Circuit _______________________________________________________________________________________ 7
Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout MAX9178
Test Circuits/Timing Diagrams (continued)
VCC + 1V EN WHEN EN = LOW OR OPEN 1.5V 1.5V VCC
0 -1V
VCC + 1V EN WHEN EN = HIGH 1.5V 1.5V 0 tPHZ OUT_+ WHEN IN_ = 2V TO VCC + 1 OUT_- WHEN IN_ = -1V TO 0.8V 50% -1V tPZH 50% 1.2V tPLZ 50% OUT_+ WHEN IN_ = -1V TO 0.8V OUT_- WHEN IN_ = 2V TO VCC + 1 tPZL 1.2V 50% VOL VOH VCC
Figure 5. High-Impedance Delay Waveform Timing
S1 CL PULSE GENERATOR IN_ 50 RL
OUT_+
OUT_-
CL
TERMINATION ONLY. ZERO CABLE LENGTH.
Figure 6. Active-to-High and High-to-Active Test Circuit
IN_
VOHUT(MIN) OUT_+ OUT_VOLUT(MAX) tAH RL DISCONNECTED tHA RL CONNECTED
Figure 7. Active-to-High and High-to-Active Timing Diagram 8 _______________________________________________________________________________________
Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout
Detailed Description
The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption, while reducing EMI emissions and system susceptibility to noise. The MAX9178 is a 400Mbps quad differential LVDS driver that is designed for high-speed, point-to-point, and low-power applications. This device accepts LVTTL/ LVCMOS input levels and translates them to LVDS output signals. The MAX9178 generates a 2.5mA to 4.5mA output current using a current-steering configuration. This currentsteering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The driver outputs are shortcircuit current limited, and enter a high-impedance state when the device is not powered or is disabled. The current-steering architecture of the MAX9178 requires a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver. Logic states are determined by the direction of current flow through the termination resistor. With a typical 3.7mA output current, the MAX9178 produces an output voltage of 370mV when driving a 100 load.
MAX9178
Table 1. Input/Output Function Table
ENABLES EN H EN L or open OUTPUT LOAD Connected INPUTS IN_ L H X OUTPUTS OUT_+ L H Z OUT_H L Z
All other combinations of enable inputs
X
Z = High impedance. X = Don't care.
Table 2. Cable Lengths and Frequencies
CONDITIONS CABLE LENGTH (m) TYPICAL SWITCHING FREQUENCY (MHz) 10.75 8.5 7.8
100 cable termination, 5pF load (each output to ground), 10% to 90% duty cycle
1 2 4
Bench testing with CAT-5E unshielded twisted-pair cable showed the termination detection working for the cable lengths and frequencies listed in Table 2. Other combinations of cable length and frequency are possible. The termination detection worked with 30m of CAT-5 at 3MHz and with alternating 3MHz and 9MHz. The termination detection is prevented from working at various cable lengths, switching frequencies, and data patterns by reflections that discharge the detection circuit.
Termination
The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. The MAX9178 is optimized for point-to-point interface with 100 termination resistors at the receiver inputs. Termination resistance values may range between 90 and 132, depending on the characteristic impedance of the transmission medium. Table 1 lists the I/O functions.
Applications Information
Power-Supply Bypassing
Bypass V CC with high-frequency, surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC.
Termination Detection
The MAX9178 has a limited-capability termination detection circuit at each output that drives the output high when the output termination is removed (or is not present at power-up), and starts the output switching when a termination is connected. These circuits prevent EMI and crosstalk that occur (due to reflections) if an unterminated line is driven.
Differential Traces
Output trace characteristics affect the performance of the MAX9178. Use controlled-impedance traces to match trace impedance to the transmission medium. Eliminate reflections and ensure that noise couples as common mode by running the differential trace pairs close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation.
_______________________________________________________________________________________
9
Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout MAX9178
Maintain the distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities.
IEC 61000-4-2 Level 4 ESD Protection
The IEC 61000-4-2 standard specifies ESD tolerance for electronic systems. The IEC 61000-4-2 model (Figure 8) specifies a 150pF capacitor that is discharged into the device through a 330 resistor. The MAX9178 outputs are rated for IEC 61000-4-2 level 4 (8kV Contact Discharge and 15kV Air Discharge). The Human Body Model (HBM, Figure 9) specifies a 100pF capacitor that is discharged into the device through a 1.5k resistor. The IEC 61000-4-2 circuit discharges higher peak current and more energy than the HBM circuit due to the lower series resistance and larger capacitor.
Cables and Connectors
Transmission media should have a nominal differential impedance of 100. To minimize impedance discontinuities, use cables and connectors that have matched differential impedance. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver.
Overshoot and Undershoot Voltage Protection
The MAX9178 is designed to protect the inputs (IN_, EN, and EN) against latchup due to transient overshoot and undershoot voltage. If the input voltage goes above VCC or below GND by up to 1V, an internal circuit limits input current to 1.5mA.
Board Layout
A four-layer PC board that provides separate power, ground, LVDS signals, and input signals is recommended. Separate the LVTTL/LVCMOS and LVDS signals to prevent coupling.
RC 50 TO 100 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 330 DISCHARGE RESISTANCE DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE
RC 1M CHARGE-CURRENTLIMIT RESISTOR
RD 1.5k DISCHARGE RESISTANCE DEVICE UNDER TEST
Cs 150pF
STORAGE CAPACITOR
Cs 100pF
STORAGE CAPACITOR
Figure 8. IEC 61000-4-2 Contact Discharge ESD Test Model
Figure 9. Human Body ESD Test Model
10
______________________________________________________________________________________
Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout
Functional Diagram
OUT1+ IN1 OUT1-
Chip Information
TRANSISTOR COUNT: 1089 PROCESS: CMOS
MAX9178
OUT2+ IN2 OUT2-
OUT3+ IN3 OUT3-
OUT4+ IN4 OUT4-
EN EN
______________________________________________________________________________________
11
Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout MAX9178
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
12
______________________________________________________________________________________
Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX9178
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
______________________________________________________________________________________
13
Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout MAX9178
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
TSSOP4.40mm.EPS

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